Understanding the defect levels of a semiconductor device during early use and the expected lifetime before wear out failure is important in many respects. This is the first experience a customer will have with the early reliability of a particular device. High temperature op-life (“HTOL”) may confirm product life capability. ATE Test and accelerated stress tests are classic methods employed to reduce early failure rates. For the extrinsic residual defects, one must be able to estimate the level defects, for example DPPM, which remain prior to product shipment to customers. Until the defect levels are acceptable, cycles of accelerated stress evaluation and defect screening or reduction are necessary. The synergy between effective test methods and process improvements are driven by the results from accelerated stress tests.